320 Keysight M8000 Series of BER Test Solutions User Guide
6 Setting up Analyzer
CDR it is the best practice to use its recovered clock output instead of the
M8020A/M8030A’s built in CDR. Choose a low loop bandwidth to measure
the jitter on an incoming data stream as the CDR will track the incoming
jitter up to the loop bandwidth and thus make it invisible to the Analyzer.
CDR Spread Spectrum Clocking
This control is used to adapt the CDR to an input bit stream with SSC.
Enabling SSC state widens the loss of lock detection window, and sets the
peaking to optimum SSC performance. Enter the Expected Deviation and
the type of deviation (Up-Spread, Down-Spread or Center-Spread) to set
the locking window to an optimum.
SSC is mostly used Down-Spread which means, the clock signal is
modulated to a lower frequency and back. Thus the average frequency is
lowered by half of the maximum deviation. The CDR is adapted to that
value. Enter the maximum deviation as specified in the standard.
CDR Setup in M8020A/M8030A
The M8020A/M8030A has an internal CDR. Follow the given steps to
perform a CDR Setup:
1Go to the Menu Bar > Analyzer and then select Data In.
2 Select CDR functional block from the Parameters window. The
following parameters will appear:
3Click CDR State switch to turn on the CDR state.
4 Specify the CDR parameters setting. For details on CDR parameters,
refer to .M8020A/M8030A CDR Parameters on page 321.
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