50 Keysight M8000 Series of BER Test Solutions User Guide
2 Know Your Hardware
M8061A Front Panel Connector Inputs/Outputs
Table 21 Electrical Idle Input
Table 22 Clock Inputs/Output
Table 23 DMI/CMI Inputs
Table 24 Data Inputs/Outputs
The inputs of the M8061A module are sensitive to static electricity.
Therefore, take necessary anti-static precautions, such as wearing a
grounded wrist strap, to minimize the possibility of electrostatic damage.
Component Description
Electrical Idle In This input is used to enable/disable the output signal by an external control signal. If the input level
is above the threshold level the module enters electrical idle. Normal operation resumes when the
input level is below the threshold (SMA, female).
Component Description
Clk Out Reference clock output used in clean clock mode to provide the synthesizer signal to the J-BERT
without external splitter (3.5 mm, female).
Clk In Reference clock input used in clean clock mode, the synthesizer should be connected to this port
(3.5 mm, female).
Aux Clk In External clock input in the range of 150 MHz to 14.2 GHz. This input is used with the J-BERT’s
internal clock. In presence of jitter, this provides the same jitter as the data outputs (3.5 mm,
female).
Component Description
DMI In Differential mode interference input independent of ground (SMA, female).
CMI In Common mode interference input relative to ground (SMA, female).
Component Description
Data Out and /Data Out Differential or single-ended data output (2.4 mm, female).
Data In x Single-ended data input (3.5 mm, female).
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