274 Keysight M8000 Series of BER Test Solutions User Guide
5 Setting up Generator
Clk/2 Jitter
This text field allows manual entry of the Clk/2 Jitter at the Data Out port
in units of seconds. It provides half rate clocking; the clock at the clock
output runs at half the bit rate.
Data Polarity Inverted
Use this option to invert the logic of the data outputs (Data Out, Trigger
Out and Clock Out).
Transition Time
Use this option to control the transition time of the output signal. The
choices are smooth, moderate and steep.
Note that the transition time is not supported by M8040A.
Setting up Output Timing
The Output Timing functional block provides following parameters:
• Data Rate - Sets the channel data rate in b/s. To set up the data rate,
go to Clock Generator and set the Frequency.
• Delay - Controls the data delay of the output signal. This also affects
the channel‘s Clock Out signal when the clock source is configured as
Data Clock.
• Jitter Delay - Controls the delay of jitter profile. Use this option to
adjust the jitter phase between multiple outputs (e.g. clock and data)
on the receiving side to ensure error free sampling for the jitter
frequencies and amplitudes used in the setup.
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