318 Keysight M8000 Series of BER Test Solutions User Guide
6 Setting up Analyzer
Clock Setup
To measure the Bit Error Rate with the Analyzer, the bit rate of the data
stream must be known. Depending on the options the instrument is
delivered with, you could use either an external clock source for the
Analyzer (for example, the clock from the generator), or extract the clock
signal from the incoming data (CDR mode).
CDR mode does not work for all kinds of data patterns. For example, if the
device under test sends only blocks of ones and zeros, there are no
transitions in the data stream and the M8020A/M8030A cannot recover
the clock.
Also, if you are testing bursts, there are some special considerations for
setting up CDR.
How does Clock Data Recovery Work?
In CDR mode, the CDR has to recover the clock from the incoming data. To
do this, the hardware has to decide whether the voltage at the input
connector is a logical '1' or '0' and then recover the clock from the
detected transitions.
Clock Data Recovery (CDR) is a special kind of Phase Locked Loop (PLL),
which recovers clock signal of a data stream. It is a regulatory loop, which
synchronizes the local oscillator with an external reference, in this case the
incoming data stream.
Phase Locked Loop
A PLL has three parts: a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector has two inputs, and one
output, which is proportional to the phase difference of the inputs. The
loop filter is a low pass filter which attenuates the higher frequencies from
the output of the phase detector. The VCO is an adjustable oscillator which
changes the output frequency depending on its input voltage. The diagram
below shows a simple PLL.
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