Renesas RL78 Series - Page 1205

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1173
Dec 10, 2015
(9) LIN/UART Mode Register (LMDn)
Address: F06C8H
7 6 5 4 3 2 1 0
— — LRDNFS — — — LMD[1:0]
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
1, 0 LMD[1:0] LIN/UART Mode Select
b1 b0
0 1: UART mode
R/W
4 to 2 — Reserved These bits are always read as 0. The write value should always
be 0.
R/W
5 LRDNFS LIN Reception Data Noise
Filtering Disable
0: The noise filter is enabled.
1: The noise filter is disabled.
R/W
6 — Reserved This bit is always read as 0. The write value should always be
0.
R/W
7 — Reserved This bit is always read as 0. The write value should always be
0.
R/W
Set the LMDn register when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
LMD[1:0] bits (LIN/UART mode select bits)
The LMD bits select the LIN/UART module mode.
To use the LIN/UART module as UART, set these bits to 01b.
With 01b set, the LIN/UART module operates as UART.
LRDNFS bit (LIN reception data noise filtering disable bit)
The LRDNFS bit enables or disables the noise filter when receiving data.
With 0 set, the noise filter is enabled when receiving data.
With 1 set, the noise filter is disabled when receiving data.