Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1175
Dec 10, 2015
UPS[1:0] bit (UART parity select bit)
The UPS bits set the parity for UART communication.
With 00b set, no parity is used in communication.
 Transmission
A parity bit is not appended to transmission data.
 Reception
A parity bit is not appended to reception data, thus causing no parity error.
With 01b set, an even parity is used in communication.
 Transmission
When the number of 1s in transmission data is odd, 1 is appended as the parity bit, whereas when the number of 1s
in the transmission data is even, 0 is appended as the parity bit.
 Reception
When the number of 1s in the received data including the parity bit is odd, the parity error occurs.
With 10b set, 0-parity is used in communication.
 Transmission
A 0 is appended as the parity bit irrespective of the number of 1s in the transmission data.
 Reception
No parity error is caused since the value of the parity bit is not checked.
With 11b set, an odd parity is used in communication.
 Transmission
When the number of 1s in transmission data is odd, 0 is appended as the parity bit, whereas when the number of 1s
in the transmission data is even, 1 is appended as the parity bit.
 Reception
When the number of 1s in the received data including the parity bit is even, the parity error occurs.
URPS bit (UART input polarity select bit)
The URPS bit sets the input polarity in UART communication.
With 0 set, the reception data is input as is.
With 1 set, the reception data is reversed before being input.
The setting of this bit applies to all the bits for the UART frames.
In half-duplex communication, set this bit and the UTPS bit to the same value.
UTPS bit (UART output polarity select bit)
The UTPS bit sets the output polarity in UART communication.
With 0 set, the transmission data is output as is.
With 1 set, the transmission data is reversed before being output.
The setting of this bit applies to all the bits for the UART frames.
In half-duplex communication, set this bit and the URPS bit to the same value.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit