Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 848
Dec 10, 2015
Figure 15-36. Procedure for Resuming Master Reception
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), mn = 00, 01, 10, 11
Starting setting for resumption
Port manipulation
Changing setting of the SPSm register
Changing setting of the SDRmn register
Changing setting of the SMRmn register
Changing setting of the SOm register
Port manipulation
Writing to the SSm register
Starting communication
Disable clock output of the target
channel by setting a port register and a
port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change the
transfer baud rate setting.
Re-set the register to change serial
mode register mn (SMRmn) setting.
Set the initial output level of the serial
clock (CKOmn).
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
and set the SEmn bit to 1 (to enable
o
p
eration
)
.
Set dummy data to the SDRmn register and
start communication.
(
Essential
)
(
Selective
)
(Selective)
(
Selective
)
(Selective)
(
Essential
)
(Essential)
(Essential)
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
(Selective)
Changing setting of the SCRmn register
If the FEF, PEF, or OVF flag remains
set, clear this using serial flag clear
trigger register mn (SIRmn).
(
Selective
)
Clearing error flag

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit