General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351
1044/1830 DocID024597 Rev 5
31.4.11 TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
31.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF FFFF
Bit 31 Value depends on IUFREMAP in TIMx_CR1.
If UIFREMAP = 0
CNT[31]: Most significant bit of counter value (on TIM2 and TIM5)
Reserved on other timers
If UIFREMAP = 1
UIFCPY: UIF Copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register
Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 and TIM5)
Bits 15:0 CNT[15:0]: Least significant part of counter value
1514131211109876543210
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR[31:16] (depending on timers)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5)
Bits 15:0 ARR[15:0]: Low Auto-reload Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 31.3.1: Time-base unit on page 984 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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