DocID024597 Rev 5 1173/1830
RM0351 Independent watchdog (IWDG)
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36.3.3 Hardware watchdog
If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and generates a reset unless the Key register is
written by the software before the counter reaches end of count or if the downcounter is
reloaded inside the window.
36.3.4 Low-power freeze
Depending on the IWDG_STOP and IWDG_STBY options configuration, the IWDG can
continue counting or not during the Stop mode and the Standby mode respectively. If the
IWDG is kept running during Stop or Standby modes, it can wake up the device from this
mode. Refer to Section : User and read protection option bytes for more details.
36.3.5 Behavior in Stop and Standby modes
Once running, the IWDG cannot be stopped.
36.3.6 Register access protection
Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To
modify them, you must first write the code 0x0000 5555 in the IWDG_KR register. A write
access to this register with a different value will break the sequence and register access will
be protected again. This implies that it is the case of the reload operation
(writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value or the window value is on going.
36.3.7 Debug mode
When the microcontroller enters debug mode (core halted), the IWDG counter either
continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in
DBG module.
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