DocID024597 Rev 5 1799/1830
RM0351 Debug support (DBG)
1807
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_TI
M17_ST
OP
DBG_TI
M16_ST
OP
DBG_TI
M15_ST
OP
rw rw rw
1514131211109876543 2 1 0
Res. Res.
DBG_
TIM8_
STOP
Res.
DBG_
TIM1_
STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 counter stopped when core is halted
0: The clock of the TIM17 counter is fed even if the core is halted
1: The clock of the TIM17 counter is stopped when the core is halted
Bit 17 DBG_TIM16_STOP: TIM16 counter stopped when core is halted
0: The clock of the TIM16 counter is fed even if the core is halted
1: The clock of the TIM16 counter is stopped when the core is halted
Bit 16 DBG_TIM15_STOP: TIM15 counter stopped when core is halted
0: The clock of the TIM15 counter is fed even if the core is halted
1: The clock of the TIM15 counter is stopped when the core is halted
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DBG_TIM8_STOP: TIM8 counter stopped when core is halted
0: The clock of the TIM8 counter is fed even if the core is halted
1: The clock of the TIM8 counter is stopped when the core is halted
Bit 12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 counter stopped when core is halted
0: The clock of the TIM1 counter is fed even if the core is halted
1: The clock of the TIM1 counter is stopped when the core is halted
Bits 10:0 Reserved, must be kept at reset value.
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