Debug support (DBG) RM0351
1798/1830 DocID024597 Rev 5
48.16.5 Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
Address: 0xE004 200C
Power on reset (POR): 0x0000 0000
System reset: not affected
Access: Only 32-bit access are supported.
48.16.6 Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
Address: 0xE004 2010
Power on reset (POR): 0x0000 0000
System reset: not affected
Access: Only 32-bit access are supported.
Bit 2 DBG_TIM4_STOP: TIM4 counter stopped when core is halted
0: The counter clock of TIM4 is fed even if the core is halted
1: The counter clock of TIM4 is stopped when the core is halted
Bit 1 DBG_TIM3_STOP: TIM3 counter stopped when core is halted
0: The counter clock of TIM3 is fed even if the core is halted
1: The counter clock of TIM3 is stopped when the core is halted
Bit 0 DBG_TIM2_STOP: TIM2 counter stopped when core is halted
0: The counter clock of TIM2 is fed even if the core is halted
1: The counter clock of TIM2 is stopped when the core is halted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
LPTIM2
_STOP
Res. Res. Res.
DBG_I
2C4_S
TOP
Res.
rw rw
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 DBG_LPTIM2_STOP: LPTIM2 counter stopped when core is halted
0: The counter clock of LPTIM2 is fed even if the core is halted
1: The counter clock of LPTIM2 is stopped when the core is halted
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 DBG_I2C4_STOP: I2C4 SMBUS timeout counter stopped when core is halted (Reserved on
STM32L475xx/476xx/486xx devices, must be kept at reset value)
0: Same behavior as in normal mode
1: The I2C4 SMBus timeout is frozen
Bit 0 Reserved, must be kept at reset value.
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