DocID024597 Rev 5 1797/1830
RM0351 Debug support (DBG)
1807
Bit 31 DBG_LPTIM1_STOP: LPTIM1 counter stopped when core is halted
0: The counter clock of LPTIM1 is fed even if the core is halted
1: The counter clock of LPTIM1 is stopped when the core is halted
Bits 30:27 Reserved, must be kept at reset value.
Bit 26 DBG_CAN2_STOP: bxCAN2 stopped when core is halted (Reserved on
STM32L475xx/476xx/486xx devices, must be kept at reset value)
0: Same behavior as in normal mode
1: The bxCAN2 receive registers are frozen
Bit 25 DBG_CAN_STOP: bxCAN1 stopped when core is halted
0: Same behavior as in normal mode
1: The bxCAN1 receive registers are frozen
Bit 24 Reserved, must be kept at reset value.
Bit 23 DBG_I2C3_STOP: I2C3 SMBUS timeout counter stopped when core is halted
0: Same behavior as in normal mode
1: The I2C3 SMBus timeout is frozen
Bit 22 DBG_I2C2_STOP: I2C2 SMBUS timeout counter stopped when core is halted
0: Same behavior as in normal mode
1: The I2C2 SMBus timeout is frozen
Bit 21 DBG_I2C1_STOP: I2C1 SMBUS timeout counter stopped when core is halted
0: Same behavior as in normal mode
1: The I2C1 SMBus timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Independent watchdog counter stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Window watchdog counter stopped when core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
Bit 10 DBG_RTC_STOP: RTC counter stopped when core is halted
0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
Bits 9:6 Reserved, must be kept at reset value.
Bit 5 DBG_TIM7_STOP: TIM7 counter stopped when core is halted
0: The counter clock of TIM7 is fed even if the core is halted
1: The counter clock of TIM7 is stopped when the core is halted
Bit 4 DBG_TIM6_STOP: TIM6 counter stopped when core is halted
0: The counter clock of TIM6 is fed even if the core is halted
1: The counter clock of TIM6 is stopped when the core is halted
Bit 3 DBG_TIM5_STOP: TIM5 counter stopped when core is halted
0: The counter clock of TIM5 is fed even if the core is halted
1: The counter clock of TIM5 is stopped when the core is halted
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