ST STM32L4 5 Series - Page 1814

Revision history RM0351
1814/1830 DocID024597 Rev 5
08-Dec-2015
3
(continued)
Removed bit TIF from Section 32.6.4: TIM16/TIM17
status register (TIMx_SR).
Removed bit TG from Section 32.6.5: TIM16/TIM17
event generation register (TIMx_EGR).
Updated reset value to 0xFFFF in Section 32.6.10:
TIM16/TIM17 auto-reload register (TIMx_ARR).
TIM6/TIM7
Updated reset value to 0xFFFF in Section 33.4.8:
TIM6/TIM7 auto-reload register (TIMx_ARR).
LPTIM
Added Section 34.5: LPTIM low power modes.
RTC
Updated reference to TAMPTS bit in Section 38.3.13:
Time-stamp function.
Updated Table 206: Effect of low-power modes on RTC.
I2C
Updated Table 223: Effect of low-power modes on the
I2C.
Updated Table 535: STM32L4x6Cat. 2 devices I2C
implementation.
USART
Replaced nCTS by CTS - nRTS by RTS - SCLK by CK.
Replaced "w" by "rc_w1" in Section 40.8.9: Interrupt flag
clear register (USART_ICR).
Updated Table 232: Effect of low-power modes on the
USART.
Updated RTOF bit description in Section 40.8.8:
Interrupt and status register (USART_ISR).
LPUART
Replaced nCTS by CTS - nRTS by RTS.
Updated Table 239: Effect of low-power modes on the
LPUART.
SWPMI
Updated Table 252: Effect of low-power modes on
SWPMI.
SDMMC
Updated limit from 48 to 50 MHz in Section 45.1:
SDMMC main features, Section 45.3: SDMMC
functional description, Section 45.8.1: SDMMC power
control register (SDIO_POWERSDMMC_POWER),
Section 45.8.2: SDMMC clock control register
(SDIO_CLKCRSDMMC_CLKCR) and in Section 45.8.4:
SDMMC command register
(SDIO_CMDSDMMC_CMD).
USB
Updated Section : Choosing the value of TRDT in
OTG_GUSBCFG.
Table 327. Document revision history (continued)
Date Revision Changes