DocID024597 Rev 5 1815/1830
RM0351 Revision history
1823
08-Dec-2015
3
(continued)
Updated TRDT bit description in Section 47.15.4: OTG
USB configuration register (OTG_GUSBCFG).
Added Table 299: TRDT values(FS).
Updated access type of bit PENA in Section 47.15.26:
OTG Host port control and status register (OTG_HPRT).
Changed bit 15 to reserved in Section 47.15.32: OTG
device configuration register (OTG_DCFG).
DEBUG
Updated REV_ID description in Section 48.6.1: MCU
device ID code.
SIGNATURE
Updated UID in Section 49.1: Unique device ID register
(96 bits).
03-Jun-2016 4
FLASH:
Updated Section 2.6: Boot configuration.
Added Caution:.
Added Note:.
FIREWALL:
Updated Section 4.4.6: Volatile data segment length
(FW_VDSL).
RCC:
Updated Section 6.2.11: Clock security system on LSE.
Updated Section 6.2.13: RTC clock.
EXTI:
Updated EXTI_IMR2 in Table 60: Extended
interrupt/event controller register map and reset values.
DMA:
Updated Table 44: Programmable data width & endian
behavior (when bits PINC = MINC = 1).
Updated Section 11.5.2: DMA interrupt flag clear
register (DMA_IFCR).
Updated Section 11.5.4: DMA channel x number of data
register (DMA_CNDTRx) (x = 1..7, where x = channel
number).
CRC:
Fixed IDR bitfield length in Section 15.4.2: Independent
data register (CRC_IDR).
FSMC:
Updated Section 16.3: AHB interface introduction.
Updated BUSTURN bit description in Section :
SRAM/NOR-Flash chip-select timing registers 1..4
(FMC_BTR1..4).
Added note 2.
Updated Section 16.6.5: NAND Flash prewait
functionality.
Updated MEMHOLD bit description in Section :
Common memory space timing register 2..4
(FMC_PMEM).
Table 327. Document revision history (continued)
Date Revision Changes
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