ST STM32L4 5 Series - Page 1816

Revision history RM0351
1816/1830 DocID024597 Rev 5
03-Jun-2016
4
(continued)
ADC:
Replaced ADVREGRN by ADVREGEN in
Section : Software procedure to calibrate the ADC and
Section 18.3.9: ADC on-off control (ADEN, ADDIS,
ADRDY).
Updated Section 18.3.9: ADC on-off control (ADEN,
ADDIS, ADRDY).
DAC:
Updated Section 19.2: DAC main features.
Updated Section 19.3.11: DAC channel buffer
calibration.
Updated CAL_FLAG1 and CAL_FLAG2 bits description
in Section 19.5.14: DAC status register (DAC_SR).
DFSDM:
Replaced DFSDM by DFSDM1 when referring to
DFSDM within other sections of the document.
Renamed DFSDM signal names in all the document.
Updated Section 24.2: DFSDM main features.
Updated Section 24.4.2: DFSDM pins and internal
signals.
Updated entire Section 24: Digital filter for sigma delta
modulators (DFSDM) to better differentiate the filter
indexes (FLTx) from the channel indexes (CHy).
LCD:
Updated Section 25.3.5: Voltage generator and contrast
control.
Updated Table 343: Remapping capability.
Updated LCDEN bit description in Section 25.6.1: LCD
control register (LCD_CR).
TIM1/TIM8:
Added note 1.
Updated Section 30.3.4: External trigger input.
Added note Note:.
Updated Section 30.3.24: Timer input XOR function.
Updated Section 30.3.29: Debug mode.
Updated OC1CE bit description in Section 30.4.7:
TIM1/TIM8 capture/compare mode register 1
(TIMx_CCMR1).
Updated ETRSEL bit description in Section 30.4.26:
TIM1 option register 2 (TIM1_OR2), Section 30.4.27:
TIM1 option register 3 (TIM1_OR3) and
Section 30.4.28: TIM8 option register 2 (TIM8_OR2).
TIM2/TIM3/TIM4/TIM5:
Updated Section Table 181.: TIMx internal trigger
connection.
Updated PCSC bit description in Section 31.4.11: TIMx
prescaler (TIMx_PSC).
Table 327. Document revision history (continued)
Date Revision Changes