ST STM32L4 5 Series User Manual

DocID024597 Rev 5 1817/1830
RM0351 Revision history
1823
03-Jun-2016
4
(continued)
Updated ETRSEL bit description in Section 31.4.21:
TIM2 option register 2 (TIM2_OR2)Section 31.4.22:
TIM3 option register 2 (TIM3_OR2).
TIM15/TIM16/TIM17
Added Section 32.4.20: Timer synchronization (TIM15).
TIM6/TIM7:
Updated PCSC bit description in Section 33.4.7:
TIM6/TIM7 prescaler (TIMx_PSC).
WWDG:
Updated Section 37.3: WWDG functional description.
Updated T bit description in Section 37.4.1: Control
register (WWDG_CR).
RTC:
Updated Section 38.3.1: RTC block diagram.
Added Table 205: RTC functions over modes.
Updated Section 38.3.9: Resetting the RTC.
Updated Section 38.3.15: Calibration clock output.
Added Caution at the end of Section 38.6.3: RTC control
register (RTC_CR).
I2C:
Updated Section 39.4.1: I2C block diagram.
Updated Section : I2C timings.
Updated Section 39.4.8: I2C master mode.
Added Note:
USART:
Updated Section 40.5.5: Tolerance of the USART
receiver to clock deviation.
Updated Section 40.5.10: USART LIN (local
interconnection network) mode.
Updated Section : Using Mute mode with Stop mode.
Updated Section 40.5.17: Wakeup from Stop mode
using USART.
Added bit UCESM in Section 40.8.3: Control register 3
(USART_CR3).
LPUART:
Added Table 236: Error calculation for programmed
baudrates at fck = 80 MHz.
Added Section 41.4.5: Tolerance of the LPUART
receiver to clock deviation.
Updated Section : Determining the maximum LPUART
baudrate allowing to wakeup correctly from Stop mode
when the LPUART clock source is the HSI clock.
Updated Section 41.4.11: Wakeup from Stop mode
using LPUART.
Added bit UCESM in Section 41.7.3: Control register 3
(LPUART_CR3).
Table 327. Document revision history (continued)
Date Revision Changes

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English