ST STM32L4 5 Series - Page 1818

Revision history RM0351
1818/1830 DocID024597 Rev 5
03-Jun-2016
4
(continued)
SAI:
Replaced FLTH by FLVL in entire Section 43: Serial
audio interface (SAI).
SWPMI:
Updated Section 44.3.2: SWP initialization and
activation.
USB:
Updated Section 47.1: Introduction.
Added Table 292: OTG_FS speeds supported.
Updated Section 47.8.1: Host SOFs.
Updated Section 47.8.2: Peripheral SOFs.
Updated Section 47.9: Power options.
Updated Section 47.11.3: FIFO RAM allocation.
Updated Table 294: Core global control and status
registers (CSRs).
Updated Table 298: Power and clock gating control and
status registers.
Updated Section 47.15.1: OTG control and status
register (OTG_GOTGCTL).
Updated Section 47.15.5: OTG reset register
(OTG_GRSTCTL).
Updated Section 47.15.32: OTG device configuration
register (OTG_DCFG).
Updated Section 47.16.3: Device initialization.
Updated Section 47.16.5: Device programming model.
27-Feb-2017 5
Update of the document to include support for
STM32L4x5, STM32L496xx and STM32L4A6xx.
SYSTEM AND MEMORY OVERVIEW:
Updated Section 2.1: System architecture,
Section 2.1.3: S2: S-bus, Section 2.1.4: S3, S4: DMA-
bus, Section 2.1.6: BusMatrix, Section 2.4: Embedded
SRAM, Table 3: SRAM2 organization, Section 2.6.1:
Boot configuration for STM32L475xx/476xx/486xx
devices
Added Figure 2: System architecture for
STM32L496xx/4A6xx devices, Section 2.1.5: S5:
DMA2D-bus, Figure 4: Memory map for
STM32L496xx/4A6xx devices, Table 2:
STM32L496xx/4A6xx devices memory map and
peripheral register boundary addresses, Section 2.6.2:
Boot configuration for STM32L496xx/4A6xx devices
FLASH:
Updated Table 11: Number of wait states according to
CPU clock (HCLK) frequency
, Section : Fast
programming, Section 3.4.1: Option bytes description,
Section 3.7.8: Flash option register (FLASH_OPTR)
Table 327. Document revision history (continued)
Date Revision Changes