DocID024597 Rev 5 1819/1830
RM0351 Revision history
1823
27-Feb-2017
5
(continued)
FIREWALL:
Updated Table 19: Segment granularity and area
ranges, Section 4.4.5: Volatile data segment start
address (FW_VDSSA)
PWR:
Updated Section 5: Power control (PWR), Figure 9:
Power supply overview, Section 5.1.8: Dynamic voltage
scaling management, Table 23: Functionalities
depending on the working mode
Added Section 5.1.7: VDD12 domain, Section 5.4.24:
Power Port I pull-up control register (PWR_PUCRI),
Section 5.4.25: Power Port I pull-down control register
(PWR_PDCRI)
RCC:
Updated Section 6.2: Clocks, Table 33: Clock source
frequency, Section 6.4.2: Internal clock sources
calibration register (RCC_ICSCR), Section 6.4.3: Clock
configuration register (RCC_CFGR), Section 6.4.6:
PLLSAI2 configuration register (RCC_PLLSAI2CFGR),
Section 6.4.7: Clock interrupt enable register
(RCC_CIER), Section 6.4.8: Clock interrupt flag register
(RCC_CIFR), Section 6.4.9: Clock interrupt clear
register (RCC_CICR), Section 6.4.10: AHB1 peripheral
reset register (RCC_AHB1RSTR), Section 6.4.11: AHB2
peripheral reset register (RCC_AHB2RSTR),
Section 6.4.13: APB1 peripheral reset register 1
(RCC_APB1RSTR1), Section 6.4.14: APB1 peripheral
reset register 2 (RCC_APB1RSTR2), Section 6.4.16:
AHB1 peripheral clock enable register
(RCC_AHB1ENR), Section 6.4.17: AHB2 peripheral
clock enable register (RCC_AHB2ENR), Section 6.4.19:
APB1 peripheral clock enable register 1
(RCC_APB1ENR1), Section 6.4.20: APB1 peripheral
clock enable register 2 (RCC_APB1ENR2),
Section 6.4.23: AHB2 peripheral clocks enable in Sleep
and Stop modes register (RCC_AHB2SMENR),
Section 6.4.25: APB1 peripheral clocks enable in Sleep
and Stop modes register 1 (RCC_APB1SMENR1),
Section 6.4.26: APB1 peripheral clocks enable in Sleep
and Stop modes register 2 (RCC_APB1SMENR2),
Section 6.4.28: Peripherals independent clock
configuration register (RCC_CCIPR), Table 34: RCC
register map and reset values
Added Figure 16: Clock tree (for STM32L496xx/4A6xx
devices), Section 6.2.4: HSI48 clock (only valid for
STM32L496xx/4A6xx devices), Section 6.2.12: USB
Clock, Section 6.4.31: Clock recovery RC register
(RCC_CRRCR), Section 6.4.32: Peripherals
independent clock configuration register
(RCC_CCIPR2)
CRS: added Section 7: Clock recovery system (CRS)
(only valid for STM32L496xx/4A6xx devices)
Table 327. Document revision history (continued)
Date Revision Changes
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