ST STM32L4 5 Series User Manual

DocID024597 Rev 5 249/1830
RM0351 Reset and clock control (RCC)
278
6.4.19 APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
Address: 0x58
Reset value: 0x0000 0400 (for STM32L496xx/4A6xx devices)
0x0000 0000 (for STM32L475xx/476xx/486xx devices)
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 76543210
Res. Res. Res. Res. Res. Res. Res.
QSPI
EN
Res. Res. Res. Res. Res. Res. Res.
FMC
EN
rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIEN: Quad SPI memory interface clock enable
Set and cleared by software.
0: QUADSPI clock disable
1: QUADSPI clock enable
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCEN: Flexible memory controller clock enable
Set and cleared by software.
0: FMC clock disable
1: FMC clock enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1
EN
OPAMP
EN
DAC1
EN
PWR
EN
Res.
CAN2
EN
CAN1
EN
CRSEN
I2C3
EN
I2C2
EN
I2C1
EN
UART5
EN
UART4
EN
USART3
EN
USART2
EN
Res.
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Res. Res.
WWD
GEN
RTCA
PBEN
LCD
EN
Res. Res. Res.
TIM7
EN
TIM6EN TIM5EN TIM4EN TIM3EN
TIM2
EN
rw rw rs rw rw rw rw rw rw rw rw

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English