ST STM32L4 5 Series - Page 248

Reset and clock control (RCC) RM0351
248/1830 DocID024597 Rev 5
6.4.18 AHB3 peripheral clock enable register(RCC_AHB3ENR)
Address offset: 0x50
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
Bit 8 GPIOIEN: IO port I clock enable (This bit is reserved for STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: IO port I clock disabled
1: IO port I clock enabled
Bit 7 GPIOHEN: IO port H clock enable
Set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 4 GPIOEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled