DocID024597 Rev 5 237/1830
RM0351 Reset and clock control (RCC)
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6.4.10 AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x28
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Bit 2 MSIRDYC: MSI ready interrupt clear
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DMA2
DRST
TSC
RST
rw rw
1514131211109 8 76543210
Res. Res. Res.
CRC
RST
Res. Res. Res.
FLASH
RST
Res. Res. Res. Res. Res. Res.
DMA2
RST
DMA1
RST
rw rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 DMA2DRST: DMA2D reset (This bit is reserved for STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: No effect
1: Reset DMA2D
Bit 16 TSCRST: Touch Sensing Controller reset
Set and cleared by software.
0: No effect
1: Reset TSC
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC
Bits 11:9 Reserved, must be kept at reset value.
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