Reset and clock control (RCC) RM0351
236/1830 DocID024597 Rev 5
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res.
HSI48
RDYC
LSE
CSSC
CSSC
PLLSAI
2RDYC
PLL
SAI1
RDYC
PLL
RDYC
HSE
RDYC
HSI
RDYC
MSI
RDYC
LSE
RDYC
LSI
RDYC
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Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear (only on STM32L496xx/4A6xx devices)
This bit is set by software to clear the HSI48RDYF flag.
0: No effect
1: Clear the HSI48RDYC flag
Bit 9 LSECSSC: LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 7 PLLSAI2RDYC: PLLSAI2 ready interrupt clear
This bit is set by software to clear the PLLSAI2RDYF flag.
0: No effect
1: Clear PLLSAI2RDYF flag
Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear
This bit is set by software to clear the PLLSAI1RDYF flag.
0: No effect
1: Clear PLLSAI1RDYF flag
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag