DocID024597 Rev 5 213/1830
RM0351 Reset and clock control (RCC)
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6.2.11 Clock security system on LSE
A Clock Security System on LSE can be activated by software writing the LSECSSON bit in
the Control/status register (RCC_CSR). This bit can be disabled only by a hardware reset or
RTC software reset, or after a failure detection on LSE. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY
set by hardware), and after the RTC clock has been selected by RTCSEL.
The CSS on LSE is working in all modes except VBAT. It is working also under system reset
(excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE
clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
MSI was in PLL-mode, this mode is disabled.
In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
the software (see Clock interrupt enable register (RCC_CIER), Clock interrupt flag register
(RCC_CIFR), Clock interrupt clear register (RCC_CICR)).
The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with
RTCSEL), or take any required action to secure the application.
The frequency of LSE oscillator have to be higher than 30 kHz to avoid false positive CSS
detection.
6.2.12 USB Clock
The USB clock can be derived from either:
• The RC 48 MHz (HSI48) clock (only for STM32L496xx/4A6xx devices)
• The MSI clock when auto-trimmed by the LSE
The HSI48 48 MHz clock can be coupled to the clock recovery system allowing adequate
clock connection for the USB OTG FS in device mode (removing the need for an external
high speed or low speed crystal).
The MSI clock when auto-trimmed by the LSE, can provide a very accurate clock source
which can be used by the USB OTG FS in device mode (removing the need for an external
high speed crystal).
6.2.13 ADC clock
The ADC clock is derived from the system clock, or from the PLLSAI1 or the PLLSAI2
output. It can reach 80 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC123_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bit fields in the ADC123_CCR.
If the programmed factor is ‘1’, the AHB prescaler must be set to ‘1’.
6.2.14 RTC clock
The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain. The system must
always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK
frequency for a proper operation of the RTC.
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