Reset and clock control (RCC) RM0351
214/1830 DocID024597 Rev 5
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock:
– The RTC continues to work even if the V
DD
supply is switched off, provided the
V
BAT
supply is maintained.
• If LSI is selected as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off.
• If the HSE clock divided by a prescaler is used as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal
voltage regulator is powered off (removing power from the V
CORE
domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.
6.2.15 Timer clock
The timer clock frequencies are automatically defined by hardware. There are two cases:
1. If the APB prescaler equals 1, the timer clock frequencies are set to the same
frequency as that of the APB domain.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
6.2.16 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
6.2.17 Clock-out capability
• MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of eight clock signals can be selected as the MCO clock.
–LSI
–LSE
– SYSCLK
–HSI16
– HSI48 (for STM32L496xx/4A6xx devices)
–HSE
–PLLCLK
–MSI
The selection is controlled by the MCOSEL[2:0] (or MCOSEL[3:0] for
STM32L496xx/4A6xx devices) bits of the Clock configuration register (RCC_CFGR).
The selected clock can be divided with the MCOPRE[2:0] field of the Clock
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