DocID024597 Rev 5 257/1830
RM0351 Reset and clock control (RCC)
278
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x6C
Reset value: 0x0007 73FF (for STM32L496xx/4A6xx devices)
0x0005 32FF (for STM32L475xx/476xx/486xx devices)
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RNG
SMEN
HASHS
MEN
AES
SMEN
rw rw rw
1514131211109876543210
Res.
DCMIS
MEN
ADC
SMEN
OTGFS
SMEN
Res. Res.
SRAM2
SMEN
GPIOIS
MEN
GPIOH
SMEN
GPIOG
SMEN
GPIOF
SMEN
GPIOE
SMEN
GPIOD
SMEN
GPIOC
SMEN
GPIOB
SMEN
GPIOA
SMEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Random Number Generator clocks disabled by the clock gating during Sleep and Stop
modes
1: Random Number Generator clocks enabled by the clock gating during Sleep and Stop
modes
Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: HASH clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: HASH clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: AES clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: AES clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 15 Reserved, must be kept at reset value.
Bit 14 DCMISMEN: DCMI clock enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: DCMI clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: DCMI clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: ADC clocks enabled by the clock gating
(1)
during Sleep and Stop modes
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