ST STM32L4 5 Series - Page 258

Reset and clock control (RCC) RM0351
258/1830 DocID024597 Rev 5
Bit 12 OTGFSSMEN: OTG full speed clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USB OTG full speed clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USB OTG full speed clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM2 interface clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SRAM2 interface clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 8 GPIOISMEN: IO port I clocks enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: IO port I clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port I clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port H clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port H clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port G clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port G clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 5 GPIOFSMEN: IO port F clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port F clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port F clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port E clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port E clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port D clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port D clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port C clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port C clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port B clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port B clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port A clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: IO port A clocks enabled by the clock gating
(1)
during Sleep and Stop modes