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DocID024597 Rev 5 273/1830

RM0351 Reset and clock control (RCC)

278

6.4.32 Peripherals independent clock configuration register (RCC_CCIPR2)

(a)

Address: 0x9C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

6.4.33 RCC register map

The following table gives the RCC register map and the reset values.

Bits 6:2 Reserved, must be kept at reset value

Bit 1 HSI48RDY: HSI48 clock ready flag

Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is

enabled by software by setting HSI48ON.

0: HSI48 oscillator not ready

1: HSI48 oscillator ready

Bit 0 HSI48ON: HSI48 clock enable

Set and cleared by software.

Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.

0: HSI48 oscillator OFF

1: HSI48 oscillator ON

a. Register is present on L496/L4A6 devices only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109 8765432 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C4SEL[1:0]

rrw

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 I2C4SEL[1:0]: I2C4 clock source selection

These bits are set and cleared by software to select the I2C4 clock source.

00: PCLK selected as I2C4 clock

01: System clock (SYSCLK) selected as I2C4 clock

10: HSI16 clock selected as I2C4 clock

11: reserved

ST STM32L4 5 Series User Manual

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