ST STM32L4 5 Series User Manual

DocID024597 Rev 5 225/1830
RM0351 Reset and clock control (RCC)
278
6.4.4 PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR
Bits 1:0 SW[1:0]: System clock switch
Set and cleared by software to select system clock source (SYSCLK).
Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode.
Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in
case of failure of the HSE oscillator, depending on STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE selected as system clock
11: PLL selected as system clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV[4:0] PLLR[1:0]
PLL
REN
Res. PLLQ[1:0]
PLL
QEN
Res. Res. PLLP
PLL
PEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109 8 7 654321 0
Res. PLLN[7:0] Res. PLLM[2:0] Res. Res. PLLSRC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:27 PLLPDIV[4:0]: Main PLL division factor for PLLSAI2CLK (only for STM32L496xx/4A6xx
devices)
Set and cleared by software to control the SAI1 or SAI2 clock frequency. PLLSAI3CLK
output clock frequency = VCO frequency / PLLPDIV.
00000: PLLSAI3CLK is controlled by the bit PLLP
00001: Reserved.
00010: PLLSAI3CLK = VCO / 2
....
11111: PLLSAI3CLK = VCO / 31

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English