ST STM32L4 5 Series User Manual

Reset and clock control (RCC) RM0351
226/1830 DocID024597 Rev 5
Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock)
Set and cleared by software to control the frequency of the main PLL output clock PLLCLK.
This output can be selected as system clock. These bits can be written only if PLL is
disabled.
PLLCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8
00: PLLR = 2
01: PLLR = 4
10: PLLR = 6
11: PLLR = 8
Caution: The software has to set these bits correctly not to exceed 80 MHz on
this domain.
Bit 24 PLLREN: Main PLL PLLCLK output enable
Set and reset by software to enable the PLLCLK output of the main PLL (used as system
clock).
This bit cannot be written when PLLCLK output of the PLL is used as System Clock.
In order to save power, when the PLLCLK output of the PLL is not used, the value of
PLLREN should be 0.
0: PLLCLK output disable
1: PLLCLK output enable
Bit 23 Reserved, must be kept at reset value.
Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock).
Set and cleared by software to control the frequency of the main PLL output clock
PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLL is disabled.
PLL48M1CLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
Caution: The software has to set these bits correctly not to exceed 80 MHz on
this domain.
Bit 20 PLLQEN: Main PLL PLL48M1CLK output enable
Set and reset by software to enable the PLL48M1CLK output of the main PLL.
In order to save power, when the PLL48M1CLK output of the PLL is not used, the value of
PLLQEN should be 0.
0: PLL48M1CLK output disable
1: PLL48M1CLK output enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLP: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).
Set and cleared by software to control the frequency of the main PLL output clock
PLLSAI3CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
PLL is disabled.
(When the PLLPDIV[4:0] is set to “00000” only for STM32L496xx/4A6xx
devices)PLLSAI3CLK output clock frequency = VCO frequency / PLLP with PLLP =7, or 17
0: PLLP = 7
1: PLLP = 17
Caution: The software has to set these bits correctly not to exceed 80 MHz on
this domain.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English