DocID024597 Rev 5 227/1830
RM0351 Reset and clock control (RCC)
278
Bit 16 PLLPEN: Main PLL PLLSAI3CLK output enable
Set and reset by software to enable the PLLSAI3CLK output of the main PLL.
In order to save power, when the PLLSAI3CLK output of the PLL is not used, the value of
PLLPEN should be 0.
0: PLLSAI3CLK output disable
1: PLLSAI3CLK output enable
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can be
written only when the PLL is disabled.
VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 86
0000000: PLLN = 0 wrong configuration
0000001: PLLN = 1 wrong configuration
...
0000111: PLLN = 7 wrong configuration
0001000: PLLN = 8
0001001: PLLN = 9
...
1010101: PLLN = 85
1010110: PLLN = 86
1010111: PLLN = 87 wrong configuration
...
1111111: PLLN = 127 wrong configuration
Caution: The software has to set correctly these bits to assure that the VCO
output frequency is between 64 and 344 MHz.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Set and cleared by software to divide the PLL, PLLSAI1 and PLLSAI2 input clock before the
VCO. These bits can be written only when all PLLs are disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 <= PLLM <= 8
000: PLLM = 1
001: PLLM = 2
010: PLLM = 3
011: PLLM = 4
100: PLLM = 5
101: PLLM = 6
110: PLLM = 7
111: PLLM = 8
Caution: The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 4 to 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
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