Reset and clock control (RCC) RM0351
264/1830 DocID024597 Rev 5
6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR)
Address: 0x80
Reset value: 0x0167 7C01
Access: word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
DFSD
M1
SMEN
Res.
SAI2
SMEN
SAI1
SMEN
Res. Res.
TIM17
SMEN
TIM16
SMEN
TIM15
SMEN
rw rw rw rw rw rw
1514131211109876543210
Res.
USART
1
SMEN
TIM8
SMEN
SPI1
SMEN
TIM1
SMEN
SD
MMC1
SMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res.
SYS
CFG
SMEN
rw rw rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDM1SMEN: DFSDM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DFSDM1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: DFSDM1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2SMEN: SAI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SAI2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SAI1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM17 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM17 timer clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM17 timer clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM16 timer clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM16 timer clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM15 timer clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: TIM15 timer clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 15 Reserved, must be kept at reset value.
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