ST STM32L4 5 Series User Manual

DocID024597 Rev 5 263/1830
RM0351 Reset and clock control (RCC)
278
Bit 2 SWPMI1SMEN: Single wire protocol clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SWPMI1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SWPMI1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes (This bit is reserved for
STM32L475xx/476xx/486xx devices)
Set and cleared by software
0: I2C4 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C4 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPUART1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: LPUART1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English