DocID024597 Rev 5 327/1830
RM0351 Peripherals interconnect matrix
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Active power mode
Run, Sleep, Low-power run, Low-power sleep.
10.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC
(ADC1/ADC2/ADC3)
Purpose
General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC
triggering event.
TIMx synchronization is described in: Section 30.3.27: ADC synchronization (TIM1/TIM8).
ADC synchronization is described in: Section 18.4.18: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN).
Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].
The connection between timers and ADCs is provided in:
• Table 107: ADC1, ADC2 and ADC3 - External triggers for regular channels
• Table 108: ADC1, ADC2 and ADC3 - External trigger for injected channels
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
10.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8)
Purpose
ADC1/ADC2/ADC3 can provide trigger event through watchdog signals to advanced-control
timers (TIM1/TIM8).
A description of the ADC analog watchdog setting is provided in: Section 18.4.29: Analog
window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH,
AWD_HTx, AWD_LTx, AWDx).
Trigger settings on the timer are provided in: Section 30.3.4: External trigger input.
Triggering signals
The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC1, 2, 3) x = 1, 2,
3 (3 watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
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