Chrom-Art Accelerator™ controller (DMA2D) RM0351
380/1830 DocID024597 Rev 5
Bit 5 START: Start
This bit is set to start the automatic loading of the CLUT. This bit is automatically reset:
– at the end of the transfer
– when the transfer is aborted by the user application by setting the ABORT bit in
the DMA2D_CR
– when a transfer error occurs
– when the transfer has not started due to a configuration error or another
transfer operation already on going (data transfer or automatic foreground
CLUT transfer).
Bit 4 CCM: CLUT Color mode
These bits define the color format of the CLUT. This register can only be written when
the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
0: ARGB8888
1: RGB888
others: meaningless
Bits 3:0 CM[3: 0]: Color mode
These bits define the color format of the foreground image. These bits can only be
written when data transfers are disabled. Once the transfer has started, they are read-
only.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
others: meaningless
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