DocID024597 Rev 5 387/1830
RM0351 Chrom-Art Accelerator™ controller (DMA2D)
391
12.5.19 DMA2D line watermark register (DMA2D_LWR)
Address offset: 0x0048
Reset value: 0x0000 0000
12.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)
Address offset: 0x004C
Reset value: 0x0000 0000
12.5.21 DMA2D IP version register (DMA2D_VERR)
Address offset: 0x03F4
Reset value: 0x0000 0012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
LW[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 LW[15:0]: Line watermark
These bits allow to configure the line watermark for interrupt generation.
An interrupt is raised when the last pixel of the watermarked line has been transferred.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
DT[7:0] Res. Res. Res. Res. Res. Res. Res. EN
rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:8 DT[7: 0]: Dead Time
Dead time value in the AHB clock cycle inserted between two consecutive accesses on
the AHB master port. These bits represent the minimum guaranteed number of cycles
between two consecutive AHB accesses.
Bits 7:1 Reserved
Bit 0 EN: Enable
Enables the dead time functionality.
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