DocID024597 Rev 5 407/1830
RM0351 Extended interrupts and events controller (EXTI)
409
14.5.10 Falling trigger selection register 2 (EXTI_FTSR2)
Address offset: 0x2C
Reset value: 0x0000 0000
Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
14.5.11 Software interrupt event register 2 (EXTI_SWIER2)
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. FT38 FT37 FT36 FT35 Res. Res. Res.
rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:3 FTx: Falling trigger event configuration bit of line x (x = 35 to 38)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 7654321 0
Res. Res. Res. Res. Res. Res. Res. Res. Res.
SWI
38
SWI
37
SWI
36
SWI
35
Res. Res. Res.
rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 SWIx: Software interrupt on line x (x = 35 to 38)
If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it
is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’
to the bit).
Bits 2:0 Reserved, must be kept at reset value.
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