Extended interrupts and events controller (EXTI) RM0351
406/1830 DocID024597 Rev 5
14.5.8 Event mask register 2 (EXTI_EMR2)
Address offset: 0x24
Reset value: 0x0000 0000
Note: EM40 only applicable for STM32L496xx/4A6xx devices
14.5.9 Rising trigger selection register 2 (EXTI_RTSR2)
Address offset: 0x28
Reset value: 0x0000 0000
Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a rising edge on a configurable interrupt line occurs during a write operation to the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. EM40 EM39 EM38 EM37 EM36 EM35 EM34 EM33 EM32
rw rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value
Bits 8:0 EMx: Event mask on line x (x = 40 to 32)
0: Event request from line x is masked
1: Event request from line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. RT38 RT37 RT36 RT35 Res. Res. Res.
rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:3 RTx: Rising trigger event configuration bit of line x (x = 35 to 38)
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.
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