DocID024597 Rev 5 405/1830
RM0351 Extended interrupts and events controller (EXTI)
409
14.5.6 Pending register 1 (EXTI_PR1)
Address offset: 0x14
Reset value: undefined
14.5.7 Interrupt mask register 2 (EXTI_IMR2)
Address offset: 0x20
Reset value: 0x0000 0087 for STM32L475xx/476xx/486xx devices, 0x0000 0187 for
STM32L496xx/4A6xx devices
Note: The reset value for the direct lines (line 17, lines from 23 to 34, line 40) is set to ‘1’ in order
to enable the interrupt by default.
Note: IM40 only applicable for STM32L496xx/4A6xx devices
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109 8 7654321 0
PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:18 PIFx: Pending interrupt flag on line x (x = 22 to 18)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 PIFx: Pending interrupt flag on line x (x = 16 to 0)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a ‘1’ to the bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. IM40 IM39 IM38 IM37 IM36 IM35 IM34 IM33 IM32
rw rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value
Bits 8:0 IMx: Interrupt mask on line x (x = 40 to 32)
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
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