ST STM32L4 5 Series User Manual

Digital-to-analog converter (DAC) RM0351
640/1830 DocID024597 Rev 5
19.5.12 DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
19.5.13 DAC channel2 data output register (DAC_DOR2)
Address offset: 0x30
Reset value: 0x0000 0000
19.5.14 DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Res. Res. Res. Res. DACC1DOR[11:0]
rrrrrrrrrrrr
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. DACC2DOR[11:0]
rrrrrrrrrrrr
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
CAL_
FLAG2
DMAU
DR2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rrrc_w1
1514131211109876543210
BWST1
CAL_
FLAG1
DMAU
DR1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rrrc_w1

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English