ST STM32L4 5 Series User Manual

Digital-to-analog converter (DAC) RM0351
644/1830 DocID024597 Rev 5
Note: It represents the number of low-speed (LSI) clocks to perform a sample phase. Sampling
time = (TSAMPLE1[9:0] + 1) x T
LSI.
19.5.18 DAC Sample and Hold sample time register 2 (DAC_SHSR2)
Address offset: 0x44
Reset value: 0x0000 0000
Note: It represents the number of low-speed (LSI) clocks to perform a sample phase. Sampling
time = (TSAMPLE1[9:0] + 1) x T
LSI.
19.5.19 DAC Sample and Hold hold time register (DAC_SHHR)
Address offset: 0x48
Reset value: 0x0001 0001
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:0 TSAMPLE1[9:0]: DAC Channel 1 sample Time (only valid in sample & hold mode)
These bits can be written when the DAC channel1 is disabled or also during normal operation.
in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If
BWSTx=1, the write operation is ignored.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. TSAMPLE2[9:0]
rw rw rw rw rw rw rw rw rw rw
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:0 TSAMPLE2[9:0]: DAC Channel 2 sample Time (only valid in sample & hold mode)
These bits can be written when the DAC channel2 is disabled or also during normal operation.
in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if
BWSTx=1, the write operation is ignored.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. THOLD2[9:0]
rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. THOLD1[9:0]
rw
Bits 31:26
Reserved, must be kept at reset value.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English