Hash processor (HASH) RM0351
872/1830 DocID024597 Rev 5
HASH_HR6
Address offset: 0x328
Reset value: 0x0000 0000
HASH_HR7
Address offset: 0x32C
Reset value: 0x0000 0000
Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these
registers are forced to their reset values.
29.6.5 HASH interrupt enable register (HASH_IMR)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
rrrrrrrrrrrrrrrr
1514131211109876543210
H6
rrrrrrrrrrrrrrrr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
rrrrrrrrrrrrrrrr
1514131211109876543210
H7
rrrrrrrrrrrrrrrr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCIE DINIE
rw rw
Bits 31:2 Reserved, must be kept at reset value
Bit 1 DCIE: Digest calculation completion interrupt enable
0: Digest calculation completion interrupt disabled
1: Digest calculation completion interrupt enabled.
Bit 0 DINIE: Data input interrupt enable
0: Data input interrupt disabled
1: Data input interrupt enabled
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