Intel Arria 10 User Manual

Parameters Value Description
For manual mode, set the CTLE options through the Assignment
Editor, or modify the Quartus Settings File (.qsf), or write to the
reconfiguration registers using the Avalon Memory-Mapped
(Avalon-MM) interface.
Refer to Continuous Time Linear Equalization (CTLE) on page 452
section in Arria 10 Transceiver Architecture chapter for more
details about CTLE architecture. Refer to How to Enable CTLE and
DFE on page 456 for more details on supported adaptation
modes.
DFE adaptation mode Adaptation enabled
Manual, Disabled
Specifies the operating mode for the Decision Feedback
Equalization (DFE) block in the RX PMA.
The default value is Disabled.
For manual mode, you can set the DFE options through the
Assignment Editor, or by modifying the Quartus Settings File
(.qsf), or write to the reconfiguration registers using the Avalon-
MM interface.
Refer to the Decision Feedback Equalization (DFE) on page 454
section in the Arria 10 Transceiver PHY Architecture chapter for
more details about DFE. Refer to How to Enable CTLE and DFE on
page 456 for more details on supported adaptation modes.
Number of fixed DFE
taps
3, 7 , 11 Specifies the number of fixed DFE taps. Select the number of
taps depending on the loss in your transmission channel and the
type of equalization required.
Table 16. RX PMA Optional Ports
Parameters Value Description
Enable
rx_analog_reset_ack
port
On/Off
Enables the optional rx_analog_reset_ack output. This port
should not be used for register mode data transfers.
Enable rx_pma_clkout
port
On/Off
Enables the optional rx_pma_clkout output clock. This port is
the recovered parallel clock from the RX clock data recovery
(CDR).
(26)
Enable
rx_pma_div_clkout
port
On/Off
Enables the optional rx_pma_div_clkout output clock. The
deserializer generates this clock. Use this to drive core logic, to
drive the RX PCS-to-FPGA fabric interface, or both.
If you select a rx_pma_div_clkout division factor of 1 or 2, this
clock output is derived from the PMA parallel clock. If you select a
rx_pma_div_clkout division factor of 33, 40, or 66, this clock is
derived from the PMA serial clock. This clock is commonly used
when the interface to the RX FIFO runs at a different rate than the
PMA parallel clock frequency, such as 66:40 applications.
rx_pma_div_clkout
division factor
Disabled, 1, 2, 33, 40,
66
Selects the division factor for the rx_pma_div_clkout output
clock when enabled.
(27)
Enable
rx_pma_iqtxrx_clkout
port
On/Off
Enables the optional rx_pma_iqtxrx_clkout output clock. This
clock can be used to cascade the RX PMA output clock to the input
of a PLL.
Enable rx_pma_clkslip
port
On/Off
Enables the optional rx_pma_clkslip control input port. A rising
edge on this signal causes the RX serializer to slip the serial data
by one clock cycle, or 2 unit intervals (UI).
continued...
(26)
This clock should not be used to clock the FPGA - transceiver interface. This clock may be used
as a reference clock to an external clock cleaner.
(27)
The default value is Disabled.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
54

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex