Intel Arria 10 User Manual

Example 8. Enabling the PRBS31 pattern generator in 64-bit mode
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address x006[7:0] with the following bits: 8’b01- -
0100
3. Perform a read-modify-write to address x007[7:0] with the following bits: 8’b0000
- - - -
4. Perform a read-modify-write to address x008[7:0] with the following bits: 8’b -
001 - - - -
5. Perform a read-modify-write to address x110[7:0] with the following bits: 8’b - - -
- - 011
6. Perform a read-modify-write to address x111[5:0] with the following bits:
8'b---11000. You must read and save the value in the register 0x111[5:0] before
changing the x1_clock_source_sel setting to xN non bonding.
7. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Note: A dash (-) indicates that the corresponding bit value should not be modified during
read-modify-write.
6.16.1.3. Enabling the PRBS Data Checker in non bonded design
You must perform a sequence of read-modify-writes to the Transceiver Native PHY
reconfiguration interface to enable the PRBS checker. You must perform read-modify-
writes to addresses 0x00A, 0x00B, 0x00C, and 0x13F. To enable the PRBS checker,
follow these steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x00A with a value of 1'b1 to bit[7].
3. Perform a read-modify-write to address 0x00B according to Register Map for PRBS
Checker for bonded and non bonded designs.
4. Perform a read-modify-write to address 0x00C according to Register Map for PRBS
Checker for bonded and non bonded designs.
5. Perform a read-modify-write to address 0x13F according to Register Map for PRBS
Checker for bonded and non bonded designs.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRBS verifier write the original values back into the read-modify-
write addresses listed above.
Related Information
Steps to Perform Dynamic Reconfiguration on page 516
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex