172 Keysight M8000 Series of BER Test Solutions User Guide
4 User Interface - M8020A Display Views
• Clean Clk Out - Half-rate, or divided, clock output with no applied
jitter.
• Clk In - Pattern Generator clock input (half-rate). Connect to clock
output of M8041A.
• Clock Source - Selects the clock source (CDR, System Clock or Clock
In) for the M8062A DataIn port (Analyzer).
• CDR - Selecting "CDR" as the M8062A DataIn clock source enables the
Analyzer CDR, so that incoming data is sampled using the recovered
clock.
• Auto Re-Lock - When this feature is enabled (the default setting) the
CDR will automatically re-lock when there is a loss of lock. When it is
disabled, the CDR will only attempt to re-lock when manually initiated
by clicking on the arrow next to the Auto Re-Lock On/Off button. It
may be necessary to perform a manual re-lock after a pattern change.
• High Transition Density - For data patterns with high transition
density, such as 1010 pattern, the CDR may have trouble gaining lock.
Enabling the High Transition Density setting reduces the CDR's
internal gain to allow it to better lock on patterns with high transition
densities. It may be necessary to perform a manual CDR re-lock after a
change in the High Transition Density setting.
• Optimize - After the CDR has gained lock, certain condition changes,
such as increasing applied jitter levels, can cause the analyzer to begin
to measure errors. Executing the Optimize function causes the CDR to
perform a finer alignment adjustment, which may result in a return to
an error-free measurement.
When using the Analyzer CDR, it may take a longer time to lock and
achieve BER=0 after a frequency change than with the other clock
sources.