652 Keysight M8000 Series of BER Test Solutions User Guide
11 Appendix
D21-5_bit This pattern is used to test Fiber Channel and Gigabit Ethernet
elements. It tests random jitter (RJ) and the symmetry of logic
transitions. The pattern is composed of alternating logic highs and
lows and is repeated continuously. Disparity rules are followed.
1010101010
1010101010 (binary)
JSPAT_b8b10 This Fiber Channel Compliant (JSPAT) pattern unframed using
B8B10 format
JSPAT_bit This Fiber Channel Compliant (JSPAT) pattern unframed using BIT
format
JTPAT_b8b10 This is a Fiber Channel jitter tolerance pattern, used to test receiver
CDR to large instantaneous phase jumps.
JTPAT_bit This is a Fiber Channel jitter tolerance pattern, used to test receiver
CDR to large instantaneous phase jumps.
JTSPAT_b8b10 This Fiber Channel Compliant (JTSPAT) pattern unframed using
B8B10 format
JTSPAT_bit This Fiber Channel Compliant (JTSPAT) pattern unframed using BIT
format
K28-5_b8b10 K28.5 pattern, tests random and deterministic jitter.
K28-5_bit K28.5 pattern, tests random and deterministic jitter.
K28-7_bit This pattern is used to test Fiber Channel and Gigabit Ethernet
elements. It has a large low frequency content that is used to test
low frequency random jitter (RJ) and PLL tracking errors. The pattern
is composed of five logic highs, followed by five logic lows. This is
repeated continuously and disparity rules are followed:
11111 00000
11111 00000 (binary).
RPAT_b8b10 This is a Fiber Channel random data pattern.
RPAT_bit This is a Fiber Channel random data pattern.
SPAT_b8b10 This is a Fiber Channel supply noise stimulus test pattern.
SPAT_bit This is a Fiber Channel supply noise stimulus test pattern.
Pattern Description
To Next Page
Loading...
Need help?
General
