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RM0008 DMA controller (DMA)

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Channel configuration procedure

The following sequence should be followed to configure a DMA channelx (where x is the

channel number).

1. Set the peripheral register address in the DMA_CPARx

moved from/ to this address to/ from the memory after the peripheral event.

2. Set the memory address in the DMA_CMARx register. The data will be written to or

read from this memory after the peripheral event.

3. Configure the total number of data to be transferred in the DMA_CNDTRx register.

After each peripheral event, this value will be decremented.

4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register

5. Configure data transfer direction, circular mode, peripheral & memory incremented

mode, peripheral & memory data size, and interrupt after half and/or full transfer in the

DMA_CCRx register

6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.

As soon as the channel is enabled, it can serve any DMA request from the peripheral

connected on the channel.

Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is

generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer,

the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer

Complete Interrupt Enable bit (TCIE) is set.

Circular mode

Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC

scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.

When circular mode is activated, the number of data to be transferred is automatically

reloaded with the initial value programmed during the channel configuration phase, and the

DMA requests continue to be served.

Memory-to-memory mode

The DMA channels can also work without being triggered by a request from a peripheral.

This mode is called Memory to Memory mode.

If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as

soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register.

The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory

mode may not be used at the same time as Circular mode.

9.3.4 Error management

In case of bus error during a DMA read or a write access, the faulty channel is automatically

disabled with through a hardware clear of its EN bit in the corresponding Channel

Configuration Register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in

the DMA_IFR register is set and an interrupt is generated if the Transfer Error Interrupt

Enable bit (TEIE) in the DMA_CCRx register is set.

ST STM32F102 series User Manual

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