RM0008 Debug support (DBG)
657/690
Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are
reset by the System Reset.
● REMAP_AF_REG (@ 0x4001 0004 in STM32F10xxx MCU)
– READ: APB - No Wait State
– WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full.
Bit 26:24= SWJ_CFG[2:0]
Set and cleared by software.
These bits are used to configure the number of pins assigned to the SWJ debug port.
The goal is to release as much as possible the number of pins to be used as General
Purpose I/Os if using a small size for the debug port.
The default state after reset is “000” (whole pins assigned for a full JTAG-DP
connection). Only one of the 3 bits can be set (it is forbidden to set more than one bit).
Note: When the APB bridge write buffer is full, it takes one extra APB cycle when writing the
REMAP_AF register. This is because the deactivation of the JTAGSW pins is done in two
cycles to guarantee a clean level on the nTRST and TCK input signals of the core.
● Cycle 1: the JTAGSW input signals to the core are tied to 1 or 0 (to 1 for nTRST, TDI
and TMS, to 0 for TCK)
● Cycle 2: the GPI/O controller takes the control signals of the SWJTAG I/O pins (like
controls of direction, pull-up/down, Schmitt trigger activation, etc.).
26.4.3 Internal pull-up and pull-down on JTAG pins
It is necessary to ensure that the JTAG input pins are not floating since they are directly
connected to flip-flops to control the debug mode features. Special care must be taken with
the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-ups and pull-
downs on JTAG input pins:
● JNTRST: Internal pull-up
● JTDI: Internal pull-up
● JTMS/SWDIO: Internal pull-up
● TCK/SWCLK: Internal pull-down
Table 159. Flexible SWJ-DP pin assignment
SWJ_
CFG
[2:0]
Available debug ports
SWJ I/O pin assigned
PA1 3 /
JTMS/
SWDIO
PA14 /
JTCK/
SWCLK
PA1 5 /
JTDI
PB3 /
JTDO
PB4/
JNTRST
000
Full SWJ (JTAG-DP + SW-DP) - Reset
State
XXXXX
001
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST
XXXX
010 JTAG-DP Disabled and SW-DP Enabled X X
100 JTAG-DP Disabled and SW-DP Disabled Released
other Forbidden
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