ST STM32F102 series User Manual

RM0008 Debug support (DBG)
661/690
26.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit Instruction Register (IR) and five
Data Registers (for full details, refer to the Cortex-M3 r1p1 Technical Reference Manual
(TRM):
Table 160. JTAG debug port data registers
IR(3:0) Data register Details
1111
BYPASS
[1 bit]
1110
IDCODE
[32 bits]
ID CODE
0x3BA00477 (ARM Cortex-M3 r1p1 ID Code)
1010
DPACC
[35 bits]
Debug Port Access Register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to Table 161 for a description of the A(3:2) bits
1011
APACC
[35 bits]
Access Port Access Register
Initiates an access port and allows access to an access port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request
Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Bit 0 = RnW= Read request (1) or write request (0).
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
There are many AP Registers (see AHB-AP) addressed as the
combination of:
– The shifted value A[3:2]
– The current value of the DP SELECT register
1000
ABORT
[35 bits]
Abort Register
– Bits 31:1 = Reserved
– Bit 0 = DAPABORT: write 1 to generate a DAP abort.

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English