ST STM32F102 series

RM0008 Flexible static memory controller (FSMC)
373/690
18.5.2 Supported memories and transactions
Tabl e 7 4 below displays the supported devices, access modes and transactions.
Transactions not allowed (or not supported) by the FSMC appear in gray.
Table 74. NOR Flash/PSRAM supported memories and transactions
Device Mode R/W
AHB
data
size
Memory
data size
Allowed/
not
allowed
Comments
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
Asynchronous R 8 16 Y
Asynchronous W 8 16 N
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y
Split into 2 FSMC
accesses
Asynchronous W 32 16 Y
Split into 2 FSMC
accesses
Asynchronous
page
R - 16 N Mode is not supported
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32 16 Y
PSRAM
Asynchronous R 8 16 Y
Asynchronous W 8 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y
Split into 2 FSMC
accesses
Asynchronous W 32 16 Y
Split into 2 FSMC
accesses
Asynchronous
page
R - 16 N Mode is not supported
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32 16 Y
SRAM and
ROM
Asynchronous R
8 / 16 /
32
8 / 16 Y Use of byte lanes NBL[1:0]
Asynchronous W
8 / 16 /
32
8 / 16 Y Use of byte lanes NBL[1:0]