ST STM32F102 series User Manual

Reset and clock control (RCC) RM0008
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6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Bit 4 IOPCEN I/O port C clock enable
Set and reset by software.
0: I/O port C clock disabled
1:I/O port C clock enabled
Bit 3 IOPBEN I/O port B clock enable
Set and reset by software.
0: I/O port B clock disabled
1:I/O port B clock enabled
Bit 2 IOPAEN I/O port A clock enable
Set and reset by software.
0: I/O port A clock disabled
1:I/O port A clock enabled
Bit 1 Reserved, always read as 0.
Bit 0 AFIOEN Alternate function I/O clock enable
Set and reset by software.
0: Alternate Function I/O clock disabled
1:Alternate Function I/O clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
EN
PWR
EN
BKP
EN
Res.
CAN
EN
Res.
USB
EN
I2C2
EN
I2C1
EN
UART5E
N
UART4
EN
USART
3EN
USART
2EN
Res.
Res. rw rw rw Res. rw Res. rw rw rw rw rw rw rw Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Reserved
WWD
GEN
Reserved
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw Res. rw Res. rw rw rw rw rw rw
Bits 31:30 Reserved, always read as 0.
Bit 29 DACEN DAC interface clock enable
Set and reset by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN Power interface clock enable
Set and reset by software.
0: Power interface clock disabled
1: Power interface clock enable

ST STM32F102 series Specifications

General

Brand	ST
Model	STM32F102 series
Category	Microcontrollers
Language	English